基于Xilinx FPGA高速串行接口 设计与实现
摘 要
由于时钟抖动，扭曲，队列同步和串扰噪声和各种非理想因素，进一步完善面临巨大的挑战并行传输率。因此，串行传输，已成为高速数据传输系统在深亚微米主要选择。在串行传输系统为了实现高速信号传输，并可节约电能和降低成本，数据更倾向于使用低摆幅模式，LVDS和CML是低电压，小的摆动，差分信号的串行传输方式，所以它被广泛地应用于PCI。快递网络物理层和高速度SERDES电路。但这个标准的LVDS传输率只能达到3Gbps，以实现独立设计以满足5Gbps的要求及以上的高速PCI。表达应用，本文研究了伪标准的LVDS 121（PLVDS）和CML的启动界面的设计研究。基于传输信号的理论，非理想因素和传输线的行为的信号完整性分析；提出了考虑高速串行传输系统的电路级和版图级设计；在PLVDS结束与CML收发器电路的设计，并提出了改进方案。其中，无歪斜单端差挠度问题提高plvds收发电路，电路的性能与加速管的改进；电平转换电路的信号快速切换到低水平的高水平，没有后续电路的调整，因此，延时小；双共模反馈电流开关电路的共模电平的控制，另一个环控制输出摆幅，输出更稳定；微分预加重技术使驱动能力强、降低码间干扰。用于CML收发器的若干关键技术，有源负反馈技术和有源电感技术不仅可以有效地扩大信号的带宽，而且可以提高电路，电路的性能，降低了电路的功耗，减少了芯片的面积；均衡技术是有效减少传输线效应符号间干扰所引起的信号失真，提高信号质量。同时也采用三级结构的樱桃。胡珀限幅放大器电路，均衡电路进一步放大到比较器输出低摆幅信号可以识别的电压幅值。在本文中，0.131cm CMOS技术实现两个PCI。表达物理层PLVD和CML高速串行数据传输接口的基础上。仿真结果表明，两种接口电路的传输速率高达5Gbps，完全符合PCI Express表示应用要求。
主题词：PLVDS，CML，预加重，均衡，有源负反馈，电压比较器，失效保护
- I -
Design and implementation of high-speed serial interface based on Xilinx
FPGA
Abstract
Due to clock jitter, skew, queue synchronization and crosstalk noise and various non-ideal factors, parallel transmission rate to further improve the face enormous challenges. So that the serial transmission has become a high-speed data transmission system in deep sub-micron main choice. In the serial transmission system in order to realize the high-speed signal transmission, and can save power and reduce the cost, the data tend to use low swing mode, LVDS and CML is the low voltage, small swing, differential signal serial transmission mode, so they are widely used in PCI.Express network physical layer and high speed SerDes circuit in. But this standard LVDS transmission rate can only reach 3Gbps, in order to achieve the independent design to meet the requirements of 5Gbps and above high speed PCI.Express application, this paper studies a pseudo standard LVDS 121 (PLVDS) and a CML interface to start the design research. Based on the theory of transmission signal, the signal integrity analysis of nonideal factors and transmission line behavior; then put forward considering the high-speed serial transmission system circuit level and layout level design; at the end of the PLVDS and the CML transceiver circuit design and put forward the improvement scheme. Among them, no skew single-ended to differential deflection problem to improve the PLVDS transceiver circuit, the circuit performance is improved with the accelerating tube; level conversion circuit the signal quickly switched to a high level from low level, without a subsequent circuit is adjusted, therefore, the time delay is small; with double common-mode feedback current switching circuit in a the loop control of common mode level, another loop control output swing, the output is more stable; differential pre-emphasis technology makes stronger driving capability and reduce intersymbol interference. Several key technologies used in a CML transceiver, the active negative feedback technology and active inductor technology not only can effectively expand the bandwidth of signal, but also can improve the performance of circuit, circuit, reduce the power consumption of the circuit, reduce the area of chip; equalization technology is effective to reduce the transmission line effect and intersymbol interference caused by signal distortion, the signal quality is improved. At the same time also uses three levels of structure of Cherry.Hooper limiting amplifier circuit, the equalization circuit outputs low swing signal for further amplification to the comparator can identify the voltage amplitude. In this paper, 0.131xm CMOS technology to achieve two for PCI.Express physical layer PLVDS and CML high-speed serial data transmission interface based on. Layout simulation results show that, two kinds of interface circuit transmission rate up to 5Gbps, fully meet the requirements of PCI.Express application.
- II -
Key Words：PLVDS，CML，Pre—emphasis，Equalization，Active Negative Feedback，Limiting Amplifier，Fail—Safe
- III -
目 录
摘 要 ..................................................................................................................................... I Abstract ................................................................................................................................... II 引 言 .................................................................................................................................... 2 1绪论 ......................................................................................................................................... 3
1.1课题研究背景 .............................................................................................................. 3 1.2高速串行技术发展现状 .............................................................................................. 3 2 Virtex-5 FPGA性能和设计技术 ......................................................................................... 7
2.1 最新款FPGA产品Virtex-5 ...................................................................................... 7 2.2 FPGA 设计方法 .......................................................................................................... 9 2.3 Xilinx FPGA设计工具简介 ....................................................................................... 9 因为第二种方法便于改变和掌握，所以后面章节中所进行 在线逻辑分析多采用第二种直接插入IP核 方法进行。3 基于FPGA TS201链路口设计与实现 ................................ 11 3 基于FPGA TS201链路口设计与实现 ................................................................................ 12
3.1 TS20l链路口简介 ..................................................................................................... 12 3.2 FPGA与TS20l 硬件连接及可行性分析 ................................................................ 14 3.3 基于FPGA 高速链路口仿真设计 .......................................................................... 16 3.4高速链路口 实际硬件调试 ...................................................................................... 21 4 B3G TDD系统中RocketIO 接口 资源需求分析与设计................................................. 23 5 B3G TDD系统MAC层高速串口 实现与仿真测试 ........................................................ 27
5.1 B3G TDD系统MAC处理接口板 实现策略 ......................................................... 27
1.MAC高层协议处理模块 ..................................................................................... 28 2.数据转接模块 ....................................................................................................... 28 5.2 RocketIO接口 仿真与测试 ..................................................................................... 29
5.2.1 RocketIO 接口 仿真 ..................................................................................... 29 5.2.2 单板测试和板间测试 .................................................................................... 32 5.3 本章小结 ................................................................................................................... 35 结 论 .................................................................................................................................. 36 参 考 文 献 ............................................................................................................................ 36 附录A 附录内容名称 ............................................................................................................ 38 致 谢 .................................................................................................................................. 43
1
引 言
在数字系统的互连设计，高速串行I/O技术替代传统的并行I / O技术已成为发展趋势。与传统的并行I / O技术相比，串行方案提供了更长的距离，带宽，更低的成本和更高的可扩展性，克服了并行I/O设计缺陷。在实际设计中的应用，利用现场可编程门阵列（FPGA）高速串行接口的实现是一种低成本的方法[1]。
Xilinx的FPGA芯片的最新一代的Virtex。的Virtex系列产品5版，是第五代产品，先进的65纳米三氧化过程中使用的新技术，expressfabrie ASMBL架构。的Virtex。高速逻辑5 LXT，数字信号处理，嵌入式处理和串行链路的应用优化。与前代相比viaex FPGA，5在性能和密度有了很大的进步：速度提高31%，容量增加64%，动态功耗降低34.9%，静态功耗保持相同的低水平，减少45%的占地面积。Virtex.5 LXT芯片是建造高达24的RocketIO收发器，支持从101Mbps的3.75gbps串行数据传输速率，支持流行的高速串行I/O接口标准。本文从时钟，复位，功率控制，发送和接收逻辑和其他关键方面，讨论了利用Virtex.5 LXT芯片RocketIO的设计和高速串行传输接口的实现。Xilinx ml505开发平台实现高速串行数据传输系统基于RocketIO技术，针对1.24Gbps的高速串行传输特性。
2