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Timing Waveform of Read Cycle for Pipelined Operation(FT'X' IH(1,2)
CLK
CE0
CE1
BEn
R/W
ADDRESS
DATAOUTOE
5666drw05
Timing Waveform of Read Cycle for Flow-through Output(FT/PIPE
(1,2,6)
CLK
CE0
CE1
BEn
R/W
ADDRESS
DATAOUTOE
NOTES:
1.OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.2.ADS = VIL, CNTEN and REPEAT = VIH.
3.The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4.Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbersare for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).6."x" denotes Left or Right port. The diagram is with respect to that port.