元器件交易网http://www.77cn.com.cn
Timing Waveform of Write with Address Counter Advance(Flow-through or Pipelined Inputs) (1)
CLK
ADDRESS
INTERNALADDRESS
ADS
CNTEN
DATAIN
Timing Waveform of Counter Repeat (2,6)
ADDRESS
An
WRITETOAn+1
WRITETOAn+2
WRITETOAn+2
ADSADDRESS
An
READAn+1
READAn+2
5666drw18
READAn+2
NOTES:
1.CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.2.CE0, BEn = VIL; CE1 = VIH.
3.The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4.No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last validADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
http://www.77cn.com.cnTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.