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Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = VIL)(2)
CLK
CE0
CE1
BEn
R/W
ADDRESS
DATAIN
DATAOUT
(2)
CLK
CE0
CE1
BEn
R/WDATAIN
DATAOUT
OE
NOTES:
1.Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.2.CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3.Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4."NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.