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Pin Names
Left PortCE0L, CE1LR/WLOELA0L - A17L(6)I/O0L - I/O35LCLKLPL/FTLADSLCNTENLREPEATLBE0L - BE3L
VDDQLOPTLZZL
VDDVSSTDI(5)TDO(5)TCK(5)TMS(5)TRST(5)
INTLCOLL
INTRCOLRRight PortCE0R, CE1RR/WROERA0R - A17R(6)I/O0R - I/O35RCLKRPL/FTRADSRCNTENRREPEATRBE0R - BE3R
VDDQROPTRZZR
Names
Chip Enables (Input)(7)Read/Write Enable (Input)Output Enable (Input)Address (Input)Data Input/OutputClock (Input)
Pipeline/Flow-Through (Input)Address Strobe Enable (Input)Counter Enable (Input)Counter Repeat(3)
Byte Enables (9-bit bytes) (Input)(7)Power (I/O Bus) (3.3V or 2.5V)(1) (Input)Option for selecting VDDQX(1,2) (Input)Sleep Mode pin(4) (Input)Power (2.5V)(1) (Input)Ground (0V) (Input)Test Data InputTest Data Output
Test Logic Clock (10MHz) (Input)Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)Interrupt Flag (Output)Collision Alert (Output)
5666 tbl 01
NOTES:
1.VDD, OPTX, and VDDQX must be set to appropriate operating levels prior toapplying inputs on the I/Os and controls for that port.
2.OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3Vlevels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then thatport's I/Os and address controls will operate at 2.5V levels and VDDQX must besupplied at 2.5V. The OPT pins are independent of one another—both ports canoperate at 3.3V levels, both can operate at 2.5V levels, or either can operateat 3.3V with the other at 2.5V.
3.When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pinsthemselves (ZZx) are not affected during sleep mode. It is recommended thatboundry scan not be operated during sleep mode.
5.Due to limited pin count, JTAG is not supported in the DR-208 package.6.Address A17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x areNC's for the IDT 70T3589.
7.Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., thesignals take two cycles to deselect.